`timescale 1 ns/10 ps

module test_cpu;
   reg clk;
	reg reset;
   initial begin
      clk = 0;
   end
   initial begin
		reset = 1;
		#50 reset = 0;
      #50000 $finish;
   end
   always #10 clk = ~clk;
   CPU cpu(.CLK(clk), .reset(reset));

endmodule // Test_CPU
